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LC74732W Datasheet(PDF) 5 Page - Sanyo Semicon Device

No. de pieza LC74732W
Descripción Electrónicos  On-Screen Display Controller
Download  38 Pages
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Fabricante Electrónico  SANYO [Sanyo Semicon Device]
Página de inicio  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC74732W Datasheet(HTML) 5 Page - Sanyo Semicon Device

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LC74731W,74732W
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
min
max
Supply voltage
VDD
VDD1 and VDD2VSS – 0.3
VSS + 6.5
V
Input voltage
VIN
All input pins
VSS – 0.3
VDD1 + 0.3
V
Output voltage
VOUT
SYNCJDG, BLANK, CHARA, SEPOUT, A0 to A17,
VSS – 0.3
VDD1 + 0.3
V
CE, and OE
Allowable power dissipation
Pdmax
275
mW
Operating temperature
Topr
–30
+70
°C
Storage temperature
Tstg
–40
+125
°C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
VDD1VDD1
4.5
5.0
5.5
V
VDD2VDD2
4.5
5.0
6.5
V
Supply voltage
VDD1VDD1
2.7
5.0
5.5
V
[Only for RGB output]
VDD2VDD2
2.7
5.0
6.5
V
VIH1
CS, SIN, SCLK, SEPIN, and MUTE
0.8 VDD1
5.5
V
High-level input voltage
VIH2
RST
0.8 VDD1
VDD1 + 0.3
V
VIH3
CTRL1 and OUTMOD
0.7 VDD1
VDD1 + 0.3
V
VIH4
D0 to D7
0.8 VDD1
5.5
V
VIL1
RST, CS, SIN, SCLK, SEPIN, and MUTE
VSS – 0.3
0.2 VDD1
V
Low-level input voltage
VIL2
CTRL1 and OUTMOD
VSS – 0.3
0.3 VDD1
V
VIL3
D0 to D7
VSS – 0.3
0.2 VDD1
V
Pull-up resistor
RPU
RST, CS, SIN, SCLK, and MUTE (when the pull-up
25
50
90
k
resistor option is specified)
Composite video signal input
VIN1
CVIN and CVCR
VDD1 = 5 V
2.0
Vp-p
voltage
VIN2
SYNIN
VDD1 = 5 V
1.5
2.0
2.5
Vp-p
Input voltage
VIN3
XtalIN (when an external clock input is used)
VDD1 = 5 V
5.0
Vp-p
fin = 2 fsc, 4 fsc
The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC)
7.159
MHz
FOSC1
The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC)
14.318
MHz
Oscillator frequency
The XtalIN and XtalOUT oscillator pins (2 fsc: PAL)
8.867
MHz
The XtalIN and XtalOUT oscillator pins (4 fsc: PAL)
17.734
MHz
FOSC2
The OSCin and OSCout oscillator pins (LC oscillator)
10
MHz
Recommended Operating Conditions
Note: If the Xtalin pin is used in clock input mode, applications must take adequate input noise prevention and reduction measures.


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