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AD9525BCPZ-REEL7 Datasheet(PDF) 3 Page - Analog Devices |
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AD9525BCPZ-REEL7 Datasheet(HTML) 3 Page - Analog Devices |
3 / 48 page Data Sheet AD9525 Rev. 0 | Page 3 of 48 SPECIFICATIONS Typical is given for VDD3 = 3.3 V ± 5%; VDD3 ≤ VDD_CP ≤ 5.25 V; TA = 25°C; OUT_RSET resistor = 4.12 kΩ; CP_RSET resistor (CPRSET) = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VDD3 and TA (−40°C to +85°C) variation as listed in Table 1. REFA at 122.88 MHz, CLKIN frequency = 2949.12 MHz. CONDITIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE VDD3 3.3 V 3.3 V ± 5% VDD_CP VDD3 5.25 V Nominally 3.3 V to 5.0 V ± 5% OUT_RSET PIN RESISTOR 4.12 kΩ Sets internal biasing currents; connect to ground CP_RSET PIN RESISTOR (CPRSET RESISTOR) 5.1 kΩ Sets internal CP current range, nominally 4.8 mA (CP_LSB = 600 µA); actual current calculated by CP_LSB = 3.06/CPRSET, connect to ground; CPRSET range = 2.7 kΩ to10 kΩ TEMPERATURE RANGE, TA −40 +25 +85 °C SUPPLY CURRENT Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY CURRENT FOR VDD3 and VDD_CP PINS fCLK = 2949.12 MHz; REFA and REFB enabled at 122.88 MHz; R dividers = 2; M divider = 2; PFD = 61.44 MHz; eight LVPECL outputs at 1474.56 MHz; LVPECL 780 mV mode VDD3 (Pin 3, Pin 36, Pin 41, Pin 46), Total Supply Voltage for Outputs 310 369 mA Outputs terminated with 50 Ω to VDD3 − 2 V VDD3 (Pin 9), Supply Voltage for M Divider, CLK Inputs and Distribution 98 107 mA VDD_CP (Pin 13), Supply Voltage for Charge Pump 6.6 7.6 mA VDD3 (Pin 20), Supply Voltage for PLL 53 63.4 mA VDD3 (Pin 32), Supply Voltage for SYNC_OUT 45 54 mA POWER DISSIPATION Table 3. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION, CHIP Does not include power dissipated in external resistors; all LVPECL outputs terminated with 50 Ω to VDD3 − 2 V; LVPECL 780 mV mode Power-On Default 782 871 mW No programming; default register values Typical Operation 1 1.15 1.23 W fCLK = 2949.12 MHz; REFA and REFB enabled at 122.88 MHz; R dividers = 2; M divider = 2; PFD = 61.44 MHz; eight LVPECL outputs at 1474.56 MHz Typical Operation 2 1.17 1.25 W fCLK = 2949.12 MHz; PLL on; REFA enabled at 122.88 MHz; M divider = 1; PFD = 122.88MHz; eight LVPECL outputs at 2949.12 MHz PD Power-Down 51 56.4 mW PD pin pulled low PD Power-Down, Maximum Sleep 13.2 19.1 mW PD pin pulled low; power-down distribution reference, Reg. 0x230[1] = 1b; note that powering down distribution reference disables safe power- down mode (see Power-Down Modes section) VDD_CP Supply 22 25 mW PLL operating; typical closed-loop configuration |
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