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AD5305ARM Datasheet(PDF) 2 Page - Analog Devices |
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AD5305ARM Datasheet(HTML) 2 Page - Analog Devices |
2 / 20 page REV. F –2– AD5305/AD5315/AD5325–SPECIFICATIONS (V DD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.) A Version 2 B Version 2 Parameter 1 Min Typ Max Min Typ Max Unit Conditions/Comments DC PERFORMANCE 3, 4 AD5305 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed Monotonic by Design over All Codes AD5315 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed Monotonic by Design over All Codes AD5325 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±10 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed Monotonic by Design over All Codes Offset Error ±0.4 ±3 ±0.4 ±3% of FSR Gain Error ±0.15 ±1 ±0.15 ±1% of FSR Lower Deadband 20 60 20 60 mV Lower deadband exists only if offset error is negative. Offset Error Drift 5 –12 –12 ppm of FSR/ °C Gain Error Drift 5 –5 –5 ppm of FSR/ °C Power Supply Rejection Ratio 5 –60 –60 dB VDD = ±10% DC Crosstalk 5 200 200 µVR L = 2 k Ω to GND or V DD DAC REFERENCE INPUTS 5 VREF Input Range 0.25 VDD 0.25 VDD V VREF Input Impedance 37 45 37 45 k Ω Normal Operation >10 >10 M Ω Power-Down Mode Reference Feedthrough –90 –90 dB Frequency = 10 kHz OUTPUT CHARACTERISTICS 5 Minimum Output Voltage 6 0.001 0.001 V This is a measure of the minimum and maximum drive capability Maximum Output Voltage 6 VDD – 0.001 VDD – 0.001 V of the output amplifier. DC Output Impedance 0.5 0.5 Ω Short Circuit Current 25 25 mA VDD = 5 V 16 16 mA VDD = 3 V Power-Up Time 2.5 2.5 µs Coming out of Power-Down Mode. VDD = 5 V 55 µs Coming out of Power-Down Mode. VDD = 3 V LOGIC INPUTS (A0) 5 Input Current ±1 ±1 µA VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10% 0.6 0.6 V VDD = 3 V ± 10% 0.5 0.5 V VDD = 2.5 V VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10% 2.1 2.1 V VDD = 3 V ± 10% 2.0 2.0 V VDD = 2.5 V Pin Capacitance 3 3 pF LOGIC INPUTS (SCL, SDA) 5 VIH, Input High Voltage 0.7 VDD VDD + 0.3 0.7 VDD VDD + 0.3 VSMBus Compatible at VDD < 3.6 V VIL, Input Low Voltage –0.3 0.3 VDD –0.3 0.3 VDD VSMBus Compatible at VDD < 3.6 V IIN, Input Leakage Current ±1 ±1 µA VHYST, Input Hysteresis 0.05 VDD 0.05 VDD V CIN, Input Capacitance 8 8 pF Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of less than 50 ns. LOGIC OUTPUT (SDA) 5 VOL, Output Low Voltage 0.4 0.4 V ISINK = 3 mA 0.6 0.6 V ISINK = 6 mA Three-State Leakage Current ±1 ±1 µA Three-State Output Capacitance 8 8 pF |
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