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AD622AR-REEL Datasheet(PDF) 6 Page - Analog Devices |
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AD622AR-REEL Datasheet(HTML) 6 Page - Analog Devices |
6 / 11 page FREQUENCY – Hz 1000 10 0 100 10M 1k 10k 100k 1M 100 1 Figure 8. Gain vs. Frequency 30 20 0 10 10k 100 1k 10 VS = 15V G = 10 LOAD RESISTANCE – Figure 9. Output Voltage Swing vs. Load Resistance OUTPUT STEP SIZE – Volts 20 15 0 020 510 15 10 5 TO 0.1% Figure 10. Settling Time vs. Step Size (G = 1) GAIN 1000 100 1 1 1000 10 100 10 Figure 11. Settling Time to 0.1% vs. Gain, for a 10 V Step 10 0% 100 90 2V 10µV ø Figure 12. Gain Nonlinearity, G = 1, RL = 10 kΩ (20 µV = 2 ppm) G=100 G=10 G=1 G=1000 AD622 +VS –VS INPUT 20V p-p VOUT 100k 0.1% 1k 10T 10k 0.01% 10k 0.1% 11k 0.1% 1k 0.1% 100 0.1% 51.1 511 5.62k Figure 13. Settling Time Test Circuit REV. C AD622–Typical Characteristics (@ +25 C, V S = 15 V, RL = 2 k , unless otherwise noted) –6– |
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