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AD73460 Datasheet(PDF) 10 Page - Analog Devices

No. de pieza AD73460
Descripción Electrónicos  Six-Input Channel Analog Front End
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AD73460 Datasheet(HTML) 10 Page - Analog Devices

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AD73460
–10–
ARCHITECTURE OVERVIEW
The AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Every instructions can be executed in a single processor
cycle. The AD73460 assembly language uses an algebraic syntax
for ease of coding and readability. A comprehensive set of devel-
opment tools supports program development.
SERIAL PORT
SPORT 2
REF
ADC3
ANALOG FRONT END
SECTION
ADC1
ADC2
ADC4
ADC5
ADC6
EXTERNAL
ADDRESS
BUS
SERIAL PORTS
SPORT 0
SHIFTER
MAC
ALU
ARITHMETIC UNITS
MEMORY
PROGRAMMABLE
I/O
AND
FLAGS
BYTE DMA
CONTROLLER
TIMER
POWER-DOWN
CONTROL
PROGRAM
SEQUENCER
DAG 2
DATA
ADDRESS
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
DAG 1
16K DM
(OPTIONAL
8K)
16K PM
(OPTIONAL
8K)
EXTERNAL
DATA
BUS
FULL MEMORY
MODE
SPORT 1
AD73460
ADSP-2100 BASE
ARCHITECTURE
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the AD73460. The pro-
cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi-
tives are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations with 40 bits of
accumulation. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
sub routine calls and returns in a single cycle. With internal
loop counters and loop stacks, the AD73460 executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The AD73460 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
ANALOG FRONT END
The analog front end (AFE) of the AD73460 is configured as a
separate block that is normally connected to either SPORT0 or
SPORT1 of the DSP section. As it is not hardwired to either
SPORT users have total flexibility in how they wish to allocate
system resources to support the AFE. It is also possible to
further expand the number of analog input channels connected
to the SPORT by cascading an AD73360 device external to
the AD73460.
The AFE is configured as six input channels. It comprises six
independent encoder channels each featuring signal condition-
ing, programmable gain amplifier, sigma-delta A/D convertor
and decimator sections. Each of these sections is described in
further detail below. All channels share a common internal
reference whose nominal value is 1.25 V. Figure 2 shows a block
diagram of the AFE section of the AD73460. It shows six input
channels along with a common reference. Communication to all
channels is handled by the SPORT2 block which interfaces to
either SPORT0 or SPORT1 of the DSP section.


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