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AD7395AN Datasheet(PDF) 3 Page - Analog Devices

No. de pieza AD7395AN
Descripción Electrónicos  3 V, Dual, Serial Input 12-/10-Bit DACs
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD7395AN Datasheet(HTML) 3 Page - Analog Devices

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–3–
REV. 0
AD7394/AD7395
AD7395 10-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
3 V
10%
5 V
10%
Units
STATIC PERFORMANCE
Resolution
1
N
10
10
Bits
Relative Accuracy
2
INL
TA = +25°C
±1.5
±1.5
LSB max
Relative Accuracy
2
INL
TA = –40
°C, +85°C, +125°C
±2.0
±2.0
LSB max
Differential Nonlinearity
2
DNL
Monotonic
±1
±1
LSB max
Zero-Scale Error
VZSE
Data = 000H
9.0
9.0
mV max
Full-Scale Voltage Error
VFSE
TA = +25
°C, +85°C, +125°C
Data = FFFH
±42
±42
mV max
Full-Scale Voltage Error
VFSE
TA = –40°C, Data = FFFH
±48
±48
mV max
Full-Scale Tempco
3
TCVFS
–35
–35
ppm/
°C typ
REFERENCE INPUT
VREF IN Range
VREF
0/VDD
0/VDD
V min/max
Input Resistance
RREF
2.5
2.5
M
Ω typ4
Input Capacitance
3
CREF
5
5
pF typ
ANALOG OUTPUT
Output Current (Source)
IOUT
Data = 200H,
∆V
OUT = 5 LSB
1
1
mA typ
Output Current (Sink)
IOUT
Data = 200H,
∆V
OUT = 5 LSB
3
3
mA typ
Capacitive Load3
CL
No Oscillation
100
100
pF typ
LOGIC INPUTS
Logic Input Low Voltage
VIL
0.5
0.8
V max
Logic Input High Voltage
VIH
VDD–0.6
4.0
V min
Input Leakage Current
IIL
10
10
µA max
Input Capacitance
3
CIL
10
10
pF max
INTERFACE TIMING3, 5
Clock Width High
tCH
50
30
ns min
Clock Width Low
tCL
50
30
ns min
Load Pulsewidth
tLDW
30
20
ns min
Data Setup
tDS
10
10
ns min
Data Hold
tDH
30
15
ns min
Clear Pulsewidth
tCLRW
15
15
ns min
Load Setup
tLD1
30
15
ns min
Load Hold
tLD2
40
20
ns min
AC CHARACTERISTICS
Output Slew Rate
SR
Data = 000H to 3FFH to 000H
0.05
0.05
V/
µs typ
Settling Time6
tS
To
±0.1% of Full Scale
70
60
µs typ
DAC Glitch
Q
Code 7FFH to 800H to 7FFH
65
65
nV/s typ
Digital Feedthrough
Q
15
15
nV/s typ
Feedthrough
VOUT/VREF
VREF = 1.5 VDC +1 V p-p,
Data = 000H, f = 100 kHz
–63
–63
dB typ
SUPPLY CHARACTERISTICS
Power Supply Range
VDD RANGE
DNL <
±1 LSB
2.7/5.5
2.7/5.5
V min/max
Shutdown Supply Current
IDD_SD
SHDN = 0, V
IL = 0 V, No Load
0.1/1.5
0.1/1.5
µA typ/max
Positive Supply Current
IDD
VIL = 0 V, No Load
125/200
125/200
µA typ/max
Power Dissipation
PDISS
VIL = 0 V, No Load
600
1000
µW max
Power Supply Sensitivity
PSS
∆V
DD =
±5%
0.006
0.006
%/% max
NOTES
1One LSB = V
REF/4096 V for the 10-bit AD7395.
2The first two codes (000
H, 001H) are excluded from the linearity error measurement.
3These parameters are guaranteed by design and not subject to production testing.
4Typicals represent average readings measured at +25
°C.
5All input control signals are specified with t
R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last three LSBs of ground.
Specifications subject to change without notice.
(@ VREF IN = 2.5 V, –40 C < TA < +85 C/+125 C, unless otherwise noted)


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