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AD7417BR-REEL Datasheet(PDF) 5 Page - Analog Devices |
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AD7417BR-REEL Datasheet(HTML) 5 Page - Analog Devices |
5 / 20 page REV. G AD7416/AD7417/AD7418 –5– AD7416 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description 1 SDA Digital I/O. Serial bus bidirectional data. Push-pull output. 2 SCL Digital Input. Serial bus clock. 3 OTI This is a logic output. The OTI is set if the result of a conversion on Channel 0 (temperature sensor) is greater that an 8-bit word in the OTR. The signal is reset at the end of a serial read operation. Open- drain output. 4GND Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry. 5A2Digital Input. The highest programmable bit of the serial bus address. 6A1Digital Input. The middle programmable bit of the serial bus address. 7A0Digital Input. The lowest programmable bit of the serial bus address. 8VDD Positive Supply Voltage, 2.7 V to 5.5 V. AD7418 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description 1 SDA Digital I/O. Serial bus bidirectional data. Push-pull output. 2 SCL Digital Input. Serial bus clock. 3 OTI This is a logic output. The OTI is set if the result of a conversion on Channel 0 (temperature sensor) is greater that an 8-bit word in the OTR. The signal is reset at the end of a serial read operation. Open- drain output. 4GND Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry. 5AIN Analog Input Channel. The input channel is single-ended with respect to GND. The input channel can convert voltage signals in the range 0 V to VREF. The analog input channel is selected by writing to the configuration register of the AD7418 and choosing Channel 4. (See Control Byte section.) 6 REFIN Reference Input. An external 2.5 V reference can be connected to the AD7418 at this pin. To enable the on-chip reference, the REFIN pin should be tied to GND. If an external reference is connected to the AD7418, the internal reference will shut down. 7VDD Positive Supply Voltage, 2.7 V to 5.5 V. 8 CONVST Logic Input Signal. Convert start signal. The rising edge of this signal fully powers up the part. The power-up time for the part is 4 µs. If the CONVST pulse is greater than 4 µs, the falling edge of CONVST places the track-and-hold mode into hold mode and initiates a conversion. If the pulse is less than 4 µs, an internal timer ensures that the track-and-hold does not go into hold and conversion is not initiated until the power-up time has elapsed. The track-and-hold goes into track mode again at the end of conversion. (See Operating Mode section.) AD7416 PIN CONFIGURATION SOIC/MSOP TOP VIEW (Not to Scale) 8 7 6 5 1 2 3 4 SDA SCL OTI GND VDD A0 A2 AD7416 A1 AD7418 PIN CONFIGURATION SOIC/MSOP TOP VIEW (Not to Scale) 8 7 6 5 1 2 3 4 SDA SCL OTI GND CONVST VDD REFIN AIN AD7418 |
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