AD7722

–9–

REV. 0

SERIAL MODE PIN FUNCTION DESCRIPTION

Mnemonic

Pin No.

Description

DVAL/RD

5

Data Valid Logic Output. A logic high on DVAL indicates that the conversion result in the

output data register is an accurate digital representation of the analog voltage at the input to the

Σ−∆ modulator. The DVAL pin is set low for 8,192 CLKIN cycles if the analog input is overranged

and after initiating CAL, SYNC or RESET.

CFMT/DRDY

4

Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid

on the rising or falling edge of the serial clock, SCO. When CFMT is logic low—SDO is valid on the

falling edge of SCO if SFMT is Low; SDO is valid on the rising edge of SCO if SFMT is High.

When CFMT is logic high—SDO is valid on the rising edge of SCO if SFMT is Low; SDO is valid

on the falling edge of SCO if SFMT is High.

TSI/DB3

44

Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set

logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is

used when two AD7722s are connected to the same serial data bus.

DOE/DB4

43

Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO

pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic

level equals the level on TSI pin, the serial data output, SDO, is active. Otherwise, SDO will be high

impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO.

SFMT/DB5

42

Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO sig-

nal. A logic low makes the FSO output a pulse one SCO cycle wide occurring every 32 SCO cycles.

With SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of

the 16 data bit transmission.

FSI/DB6

41

Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7722 serial output

data register to an external source. When the falling edge of CLKIN detects a low to high transition,

the AD7722 interrupts the current data transmission, reloads the output serial shift register, resets

SCO, and transmits the conversion result. Synchronization starts immediately, and the next 127

conversions are invalid. In serial mode, DVAL remains high. FSI inputs applied synchronous to the

output data rate do not alter the serial data transmission. If FSI is tied to either a logic high or low,

the AD7722 will generate FSO outputs controlled by the logic level on SMFT.

SCO/DB7

40

Serial Data Clock Output. The serial clock output is synchronous to the CLKIN signal and has a

frequency one-half the CLKIN frequency. A data transmission frame is 32 SCO cycles long.

SDO/DB8

38

Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. A serial

data transmission lasts 32 SCO cycles. After the LSB is output, trailing zeros are output for the re-

maining 16 SCO cycles.

FSO/DB9

37

Frame Sync Output. This output indicates the beginning of a word transmission on the SDO pin.

Depending on the logic level of the SFMT pin, the FSO signal is either a positive pulse approxi-

mately one SCO period wide or a frame pulse, which is active low for the duration of the 16 data bit

transmission (reference Figure 4).

DGND/DB0

3

In serial mode these pins should be tied to DGND.

DGND/DB1

2

DGND/DB2

1

DGND/DB10

36

DGND/DB11

35

DGND/DB12

34

DGND/DB13

33

DGND/DB14

32

DGND/DB15

31