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AD7715ACHIPS-5 Datasheet(PDF) 3 Page - Analog Devices

No. de pieza AD7715ACHIPS-5
Descripción Electrónicos  3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD7715ACHIPS-5 Datasheet(HTML) 3 Page - Analog Devices

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Parameter
A Version
1
Unit
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
16
Bits min
Guaranteed by Design. Filter Notch
≤ 60 Hz
Output Noise
See Tables IX to XII
Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity
±0.0015
% of FSR max
Filter Notch
≤ 60 Hz
Unipolar Offset Error
See Note 2
Unipolar Offset Drift3
0.2
µV/°C typ
Bipolar Zero Error
See Note 2
Bipolar Zero Drift3
0.2
µV/°C typ
Positive Full-Scale Error4
See Note 2
Full-Scale Drift3, 5
0.2
µV/°C typ
Gain Error6
See Note 2
Gain Drift3, 7
0.2
ppm of FSR/
°C typ
Bipolar Negative Full-Scale Error2
±0.003
% of FSR max
Typically
±0.0004%
Bipolar Negative Full-Scale Drift3
1
µV/°C typ
For Gains of 1 and 2
0.6
µV/°C typ
For Gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR)
90
dB min
at DC. Typically 102 dB
Normal-Mode 50 Hz Rejection
8
98
dB min
For Filter Notches of 25 Hz, 50 Hz,
± 0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
8
98
dB min
For Filter Notches of 20 Hz, 60 Hz,
± 0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
8
150
dB min
For Filter Notches of 25 Hz, 50 Hz,
± 0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
8
150
dB min
For Filter Notches of 20 Hz, 60 Hz,
± 0.02 × f
NOTCH
Common-Mode Voltage Range
9
AGND to AVDD
V min to V max
AIN for BUF Bit of Setup Register = 0 and REF IN
Absolute AIN/REF IN Voltage
8
AGND – 30 mV
V min
AIN for BUF Bit of Setup Register = 0 and REF IN
AVDD + 30 mV
V max
Absolute/Common-Mode AIN Voltage
9
AGND + 50 mV
V min
BUF Bit of Setup Register = 1
AVDD – 1.5 V
V max
AIN DC Input Current
8
1
nA max
AIN Sampling Capacitance
8
10
pF max
AIN Differential Voltage Range
10
0 to +VREF/GAIN
11
nom
Unipolar Input Range (B/U Bit of Setup Register = 1)
±V
REF/GAIN
nom
Bipolar Input Range (B/U Bit of Setup Register = 0)
AIN Input Sampling Rate, fS
GAIN
× f
CLK IN/64
For Gains of 1 and 2
fCLK IN/8
For Gains of 32 and 128
REF IN(+) – REF IN(–) Voltage
+1.25
V nom
±1% for Specified Performance. Functional with Lower V
REF
REF IN Input Sampling Rate, fS
fCLK IN/64
LOGIC INPUTS
Input Current
±10
µA max
All Inputs Except MCLK IN
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
2.0
V min
MCLK IN Only
VINL, Input Low Voltage
0.4
V max
VINH, Input High Voltage
2.5
V min
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
0.4
V max
ISINK = 100 µA Except for MCLK OUT
12
VOH, Output High Voltage
DVDD – 0.6
V min
ISOURCE = 100 µA Except for MCLK OUT
12
Floating State Leakage Current
±10
µA max
Floating State Output Capacitance13
9
pF typ
Data Output Coding
Binary
Unipolar Mode
Offset Binary
Bipolar Mode
AD7715
AD7715-3–SPECIFICATIONS (AV
DD = +3 V, DVDD = +3 V, REF IN (+) = +1.25 V;
REF IN(–) = AGND; fCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
–3–
REV. C


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