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AD7851KN Datasheet(PDF) 5 Page - Analog Devices

No. de pieza AD7851KN
Descripción Electrónicos  14-Bit 333 kSPS Serial A/D Converter
Download  36 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

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–5–
REV. A
AD7851
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
1.6mA
+2.1V
200µA
CL
50pF
TO
OUTPUT
PIN
IOL
IOH
Figure 1. Load Circuit for Digital Output Timing
Specifications
DB15
DB0
DB11
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
6
t
9
t
10
15
6
16
t
12
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
3-STATE
3-STATE
DB15
t
CONVERT
t
CONVERT = 3.25µs MAX, t1 = 100ns MIN,
t
5 = 30ns MAX, t7 = 30ns MIN
t
1
t
6
t
7
Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC (O/P)
SCLK (O/P)
t
4
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
12
t
9
t
10
15
6
16
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
DB15
DB0
3-STATE
DB11
3-STATE
DB15
t
CONVERT
t
CONVERT = 3.25µs MAX, t1 = 100ns MIN,
t
5 = 30ns MAX, t7 = 30ns MIN
t
1
t
6
t
7
Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)


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