AD7864

–4–

REV. A

Parameter

A, B Versions

Units

Test Conditions/Comments

1.65

µs max

Conversion Time, Internal Clock

13

Clock Cycles

Conversion Time, External Clock

2.6

µs max

CLKIN = 5 MHz

0.34

µs max

Acquisition Time

No. of Channels

Selected Number of Channels Multiplied by

µs max

2

µs max

STBY Rising Edge to CONVST Rising Edge

3

6ms max

STBY Rising Edge to CONVST Rising Edge

35

ns min

CONVST Pulsewidth

70

ns min

CONVST Rising Edge to BUSY Rising Edge

Read Operation

0

ns min

CS to RD Setup Time

0

ns min

CS to RD Hold Time

35

ns min

Read Pulsewidth

4

35

ns max

Data Access Time After Falling Edge of

RD, V

40

ns max

Data Access Time After Falling Edge of

RD, V

5

5

ns min

Bus Relinquish Time After Rising Edge of

RD

30

ns max

10

ns min

Time Between Consecutive Reads

75

ns min

EOC Pulsewidth

180

ns max

70

ns max

RD Rising Edge to FRSTDATA Edge (Rising or Falling)

15

ns max

EOC Falling Edge to FRSTDATA Falling Delay

0

ns min

EOC to RD Delay

Write Operation

20

ns min

WR Pulsewidth

0

ns min

CS to WR Setup Time

0

ns min

WR to CS Hold Time

5

ns min

Input Data Setup Time of Rising Edge of

WR

5

ns min

Input Data Hold Time

NOTES

°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

µF decoupling capacitor on the V

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

TO

OUTPUT

50pF

1.6V

400 A

1.6mA

Figure 1. Load Circuit for Access Time and Bus Relinquish Time