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AD7937AR Datasheet(PDF) 1 Page - Analog Devices

No. de pieza AD7937AR
Descripción Electrónicos  LC2MOS 84 Loading Dual 12-Bit DAC
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD7937AR Datasheet(HTML) 1 Page - Analog Devices

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7937
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
LC2MOS
(8+4) Loading Dual 12-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
DAC A LS
INPUT REG
CONTROL
LOGIC
AGNDA
DAC A MS
INPUT REG
DAC A REGISTER
DAC A
48
12
UPD
DAC B LS
INPUT REG
DAC B MS
INPUT REG
DAC B REGISTER
DAC B
48
12
A1
A0
CS
WR
CLR
IOUTA
RFBA
VREFA
VREFB
RFBB
IOUTB
AGNDB
AD7937
VDD
DB7–DB0
DGND
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Surface-Mount Package
4-Quadrant Multiplication
Low Gain Error (3 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7937 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the mono-
lithic construction ensures excellent thermal tracking. Both DACs
are guaranteed 12-bit monotonic over the full temperature range.
The AD7937 has a 2-byte (eight LSBs, four MSBs) loading
structure. It is designed for right-justified data format. The control
signals for register loading are A0, A1,
CS, WR, and UPD. Data
is loaded to the input registers when
CS and WR are low. To
transfer this data to the DAC registers,
UPD must be taken
low with
WR.
Added features on the AD7937 include an asynchronous
CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance, one DAC may be operated with AGND
biased while the other is connected in the standard configuration.
The AD7937 is manufactured using the Linear Compatible
CMOS (LC
2MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC, and 5 V CMOS logic
level inputs.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications that are
not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size
The AD7937 is packaged in a small 24-lead SOIC.
3. Wide Power Supply Tolerance
The device operates on a 5 V VDD, with
±10% tolerance on
this nominal figure. All specifications are guaranteed over
this range.


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