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AD808-622BR Datasheet(PDF) 8 Page - Analog Devices

No. de pieza AD808-622BR
Descripción Electrónicos  Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
Download  12 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD808-622BR Datasheet(HTML) 8 Page - Analog Devices

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REV. 0
–8–
AD808
1
2
5
6
7
3
4
8
VEE
SDOUT
NIN
AVCC1
THRADJ
AVEE
AD808
PIN
16
15
12
11
10
14
13
9
R10
154
R9
154
R6 100
C7
R5 100
R1
100
R2
100
C1 0.1 F
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
C5 0.1 F
C2
0.1 F
R4
100
R8 100
R7 100
R3
100
C8
R12
154
TP1
TP2
R11
154
CD
TP7
SDOUT
TP5
TP6
RTHRESH
C11
10 F
C10
GND
R14
49.9
R15
49.9
C12
0.1 F
C4 0.1 F
C3 0.1 F
C6
0.1 F
J1
J2
J3
J4
+5V
TP3
TP4
NOTE: INTERCONNECT RUN
UNDER DUT
VECTOR PINS SPACED FOR RN55C
TYPE RESISTOR; COMPONENT
SHOWN FOR REFERENCE ONLY
VECTOR PINS SPACED THROUGH-HOLE
CAPACITOR ON VECTOR CUPS; COMPONENT
SHOWN FOR REFERENCE ONLY
TP8
J5
C9
R13
301
R16 3.65k
J6
J7
C13 0.1 F
C14 0.1 F
PIN
NIN
50
STRIP LINE
EQUAL LENGTH
NOTE:
C7–C10 ARE 0.1µF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS
DATAOUTN
DATAOUTP
VCC2
CLKOUTN
CLKOUTP
VCC1
CF1
CF2
AVCC2
Figure 15. Evaluation Board Schematic
Center Frequency Clamp (Figure 13)
An N-channel FET circuit can be used to bring the AD808
VCO center frequency to within
±10% of 622 MHz when
SDOUT indicates a Loss of Signal (LOS). This effectively re-
duces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. The N-FET can have “on” resistance as high
as 1 k
Ω and still attain effective clamping. However, the chosen
N-FET should have greater than 10 M
Ω “off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
VEE
SDOUT
AVCC2
PIN
NIN
AVCC1
THRADJ
AVEE
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
VCC1
CF1
CF2
VCC2
AD808
N_FET
CD
Figure 13. Center Frequency Clamp Schematic
RBW:
30Hz ST: 3.07 min RANGE: R=
0, T=
0dBm
DIV
20.00m
CD
PEAK
0.047
0.11
0.10
0.07
0.47
0.04
DIV
36.00m
START
STOP
500.000Hz
100 000.000Hz
Figure14. Jitter Transfer vs. CD


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