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AD8320 Datasheet(PDF) 11 Page - Analog Devices |
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AD8320 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 20 page  AD8320 –11– REV. 0 Basic Connection Figure 45 shows the basic schematic for operating the AD8320. Because the amplifier operates from a single supply, the input signal must be ac-coupled using a 0.1 µF capacitor. The input pin has a bias level of about 1.9 V. This bias level is available on the VREF pin (Pin 18) and can be used to externally bias signals if dc-coupling is desired. Under all conditions, a 0.1 µF decoupling capacitor must be connected to the VREF pin. If the VREF volt- age is to be used externally, it should be buffered first. The VIN pin of the AD8320 (Pin 19) has an input impedance of 220 Ω. Typically, in video applications, 75 Ω termination is favored. As a result, an external shunt resistance (R1) to ground of 115 Ω is required to create an overall input impedance of 75 Ω. If 50 Ω termination is required, a 64.9 Ω shunt resistor should be used. Note, to avoid dc loading of the VIN pin, the ac-coupling capacitor should be placed between the input pin and the shunt resistor as shown in Figure 45. On the output side, the VOUT pin also has a dc bias level. In this case the bias level is midway between the supply voltage and ground. The output signal must therefore be ac-coupled before being applied to the load. The dc bias voltage is available on the VOCM pin (Pin 5) and can be used in dc-coupled applications. This node must be decoupled to ground using a 0.1 µF capaci- tor. If the VOCM voltage is to be used externally, it should be buffered. Since the AD8320 has a dynamic output impedance of 75 Ω, no external back termination resistor is required. If the output signal is being evaluated on 50 Ω test equipment such as a spec- trum analyzer, a 75 Ω to 50 Ω adapter (commonly called a pad) should be used to maintain a properly matched circuit. Varying the Gain The gain of the AD8320 can be varied over a range of 36 dB, from –10 dB to +26 dB, by varying the 8-bit gain setting word. The timing diagram for AD8320’s serial interface is shown in Figure 43. The write cycle to the device is initiated by the falling edge of DATEN. This is followed by eight clock pulses that clock in the control word. Because the clock signal is level triggered, data is effectively clocked on the falling edge of CLK. After the control word has been clocked in, the DATEN line goes back high, allowing the gain to be updated (this takes about 30 ns). The relationship between gain and control word is given by the equation: Gain (V/V) = 0.077 × Code + 0.316 where code is the decimal equivalent of the gain control word (0 to 255). The gain in dB is given by the equation: Gain (dB) = 20 log10 (0.077 × Code + 0.316) The digital interface also contains an asynchronous power-down mode. The normally high PD line can be pulled low at any time. This turns off the output signal after 45 ns, and reduces the quiescent current to between 25 mA and 32 mA (depending upon the power supply voltage). In this mode, the programmed gain is maintained. Clock Line Feedthrough Clock feedthrough results in a 5 mV p-p signal appearing super- imposed on the output signal (see Figure 32). If this impinges upon the dynamic range of the application, the clock signal should be noncontinuous, i.e., should only be turned on for eight cycles during programming. Power Supply and Decoupling The AD8320 should be powered with a good quality (i.e., low noise) single supply of between +5 V and +12 V. In order to achieve an output power level of +18 dBm (6.2 V p-p) into C6 0.1 F CLK SDATA DATEN PD DATEN SDATA GND GND GND GND GND POWER- DOWN / SWITCH INTER. VOUT VOCM C10 0.1 F C8 0.1 F TO DIPLEXER RIN = 75 ATTENUATOR CORE DATA LATCH DATA SHIFT REGISTER CLK C5 0.1 F C4 0.1 F C7 10 F C2 0.1 F C11 0.1 F VCC +5V TO +12V VREF C12 0.1 F VIN R1* 115 C1 0.1 F INPUT C3 0.1 F REFERENCE VCC VCC VCC VCC GND BYP AD8320 *FOR A 75 INPUT IMPEDANCE PD VCC Figure 45. Basic Connection |
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