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AD8327 Datasheet(PDF) 4 Page - Analog Devices |
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AD8327 Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page REV. 0 AD8327 –4– ABSOLUTE MAXIMUM RATINGS * Supply Voltage +VS Pins 4, 6, 11, 12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltages Pins 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V Pins 1, 2, 3, 19, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V Internal Power Dissipation TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 mW Operating Temperature Range . . . . . . . . . . . –40 °C to +85°C Storage Temperature Range . . . . . . . . . . . . –65 °C to +150°C Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD8327 DATEN VIN– VIN+ GND VCC SLEEP BYP VCC VCC GND SDATA CLK GND VCC TXEN VCC VOUT GND GND CXR PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. 2 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 3 TXEN Logic “0” disables transmission. Logic “1” enables transmission. 4, 6, 11, 12, 16 VCC Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin. 5, 8, 9, 13, 15 GND Common External Ground Reference 7 CXR Transmit Enable/Disable Timing Capacitor. This pin is decoupled with a 100 pF capacitor to GND. 10 VOUT Output Signal 14 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor). 17 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. 18 VIN– Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. 19 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where ZOUT goes to 200 Ω and supply current is reduced to 5 mA. Logic 1 enables normal operation. 20 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8327 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package Description JA Package Option AD8327ARU –40 °C to +85°C 20-Lead TSSOP 85 °C/W* RU-20 AD8327ARU-REEL –40 °C to +85°C 20-Lead TSSOP 85 °C/W* RU-20 AD8327-EVAL Evaluation Board *Thermal Resistance measured on SEMI standard 4-layer board. |
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Descripción similar - AD8327 |
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