ADF4001 datasheet(8/16 Pages) AD

No. de pieza	ADF4001

Descripción Electrónicos	200 MHz Clock Generator PLL

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Fabricante Electrónico	AD [Analog Devices]

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REV. 0

ADF4001

–8–

Table III. Reference Counter Latch Map

LDP

OPERATION

0

THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1

FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

ABP2

ABP1

ANTIBACKLASH PULSEWIDTH

00

2.9ns

01

1.3ns

10

6.0ns

1

2.9ns

R14

R13

R12

..........

R3

R2

R1

DIVIDE RATIO

0

..........

0011

0

..........

0102

0

..........

0113

0

..........

1004

.

..........

....

.

..........

....

.

..........

....

1

..........

1

0

16380

1

..........

1

0

1

16381

1

..........

1

0

16382

1

..........

1

16383

TEST MODE BITS SHOULD

BE SET TO 00 FOR NORMAL

OPERATION

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

C2 (0) C1 (0)

R1

R2

R3

R4

R5

R7

R14

ABP1

T2

LDP

R13

R6

CONTROL

BITS

ABP2

T1

DB21

R12

R11

R10

DB22

DB23

R8

R9

RESERVED

TEST

MODE

BITS

ANTI-

BACKLASH

WIDTH

14-BIT REFERENCE COUNTER

XX

X

X = DON’T CARE

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