REV. 0

ADM1022

–5–

PIN FUNCTION DESCRIPTION

Pin

No.

Mnemonic

Description

1

FAN_OFF

Digital Output (Open-Drain) Fan Off Request. When asserted low this indicates a request to shut

off the fan independent of the FAN_SPD output. When negated (output FET off) it indicates that

the fan may be turned on.

2

MR

Digital Input, Manual Reset. A logic low on this input causes

RST2 to be asserted. Once this input

Ω pull-up resistor.

Leave unconnected if not used.

3

RST1

be optionally reset; external logic must be used to prevent system auxiliary reset from occurring

when used as an input.

4

GND

GROUND. Power and Signal Ground.

POWER 3.3 V. Power source and voltage monitor input for first reset generator.

Analog Input. Voltage monitor input for second reset generator.

7

RST2

Digital Output (Open-Drain). This pin is asserted low under any of the following conditions:

– while

MR is held low

– while

RST1 is asserted.

8

FAN_SPD/NTEST_IN

Analog Output/Test Input. An active-high input that enables NAND board-level connectivity testing.

Refer to section on NAND testing. Used as an analog output for fan speed control when NAND

test is not selected.

9

D1–

Remote Thermal Diode Negative Input. This is the negative input (current sink) from the remote

thermal diode. This also serves as the negative input into the A/D.

10

D1+

Remote Thermal Diode Positive Input. This is the positive input (current source) from the remote

thermal diode. This serves as the positive input into the A/D.

11

D2–/

THERM

Analog Input/Digital I/O (Open-Drain). Can be programmed as negative input for a second diode

temperature sensor, or as a digital I/O pin. In this case it is an active low thermal overload output

that indicates a violation of a temperature set point (over-temperature). Also acts as an input to

provide external fan control. When this pin is pulled low by an external signal, a status bit is set and

the fan speed is set to full on.

12

D2+/GPI

Analog/Digital Input. Can be programmed as the positive input for a second diode sensor, or as a

general-purpose logic input. In this case it can be programmed as an active high or active low input

that sets Bit 4 of the Status Registers. This bit can only be reset by reading the status registers, pro-

vided GPI is in the inactive state.

13

ADD/NTEST_OUT

Digital I/O. The lowest order programmable bit of the SMBus Address. ADD is sampled at power-

up and changing it while powered on will have no immediate effect. This pin also functions as an

output when doing a NAND test.

14

INT

Digital Output (Open Drain), System Interrupt Output. This signal indicates a violation of a set

trip point. The output is enabled when Bit 1 of the Configuration Register is set to 1. The default

state is disabled.

15

SCL

Digital Input SMBus Clock.

16

SDA

Digital I/O (Open-Drain) SMBus Bidirectional Data.