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ADMC401BST Datasheet(PDF) 9 Page - Analog Devices |
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ADMC401BST Datasheet(HTML) 9 Page - Analog Devices |
9 / 60 page ADMC401 –9– REV. B Parameter Min Max Unit Memory Write Switching Characteristics: t DW Data Setup before WR High 0.5t CK – 7 + w ns t DH Data Hold after WR High 0.25t CK – 2 ns t WP WR Pulsewidth 0.5t CK – 5 + w ns t WDE WR Low to Data Enabled 0 ns t ASW A0–A13, DMS, PMS Setup before WR Low 0.25t CK – 6 ns t DDR Data Disable before WR or RD Low 0.25t CK – 6 ns t CWR CLKOUT High to WR Low 0.25t CK – 5 0.25t CK + 7 ns t AW A0–A13, DMS, PMS, Setup before WR Deasserted 0.75t CK – 9 + w ns t WRA A0–A13, DMS, PMS Hold after WR Deasserted 0.25t CK – 3 ns t WWR WR High to RD or WR Low 0.5t CK – 5 ns w = wait states × t CK. CLKOUT A0–A13 D WR DMS, PMS RD tWRA tWWR tWP tASW tAW tDH tDDR tCWR tWDE tDW Figure 5. Memory Write |
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