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ADV7176AKS Datasheet(PDF) 9 Page - Analog Devices |
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ADV7176AKS Datasheet(HTML) 9 Page - Analog Devices |
9 / 52 page ADV7175A/ADV7176A –9– REV. B ABSOLUTE MAXIMUM RATINGS 1 VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . –65 °C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150 °C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260 °C Analog Outputs to GND 2 . . . . . . . . . . . . . GND – 0.5 to VAA NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Analog output short circuit to any power supply or common can be of an indefinite duration. ORDERING GUIDE Temperature Package Package Model Range Description Option ADV7175AKS 0 °C to +70°C Plastic Quad Flatpack S-44 ADV7176AKS 0 °C to +70°C Plastic Quad Flatpack S-44 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION WARNING! ESD SENSITIVE DEVICE 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 27 28 25 26 23 24 33 PIN 1 IDENTIFIER VREF DAC A DAC B VAA GND VAA DAC D VAA P5 P6 P7 P8 P9 P10 P11 P12 GND VAA DAC C COMP SDATA SCLOCK ADV7175A/ADV7176A PQFP TOP VIEW (Not to Scale) PACKAGE THERMAL PERFORMANCE The 44-PQFP package used for this device takes advantage of an ADI patented thermal coastline lead frame construction. This maximizes heat transfer into the leads and reduces the package thermal resistance. The junction-to-ambient ( θ JA) thermal resistance in still air on a four-layer PCB is 35.5 °C/W. The junction-to-case thermal resistance ( θ JC) is 13.75 °C/W. |
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