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DAC16 Datasheet(PDF) 11 Page - Analog Devices |
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DAC16 Datasheet(HTML) 11 Page - Analog Devices |
11 / 12 page DAC16 REV. B –11– A discrete drive circuit is used to achieve the best performance from the SD5000 quad DMOS switch. This switch-driving cell is composed of MPS571 RF NPN transistors and an MC10124 TTL-to-ECL translator. Using this technique provides both high speed and highly symmetrical drive signals for the SD5000 switches. The switches arc arranged in a single-pole, double- throw (SPDT) configuration. The 500 pF “flyback” capacitor is switched to the op amp summing junction during the hold mode to keep switching transients from feeding to the output. This ca- pacitor is grounded during sample mode to minimize its effect on acquisition time. Careful circuit layout of the high speed SHA section is almost as important as the design itself. Double-sided printed circuit board, a compact layout, and short critical signal paths all ensure best performance. Op Amp Selection When selecting the amplifier to be used for the DAC16’s I–V converter, there are two main application areas; those requiring high accuracy, and those seeking high speed. In high accuracy applications, three parameters are of prime importance: (1) input offset voltage. VOS; (2) input bias current, –IB; and (3) off- set voltage drift, TCVOS. In these applications where 16-bit performance must be maintained with an external reference at +5 V, an op amp’s input offset voltage must be less than 15 µV ( ≈0.1 LSB) with a bias current less than 6 nA. The op amp must also exhibit high open-loop gain to keep the offset voltage below this limit over the specified full-scale output range. Thus, for a maximum output of 5 V, the op amp’s open loop gain must be greater than 1300 V/mV. For low frequency, high accuracy applications, Table IV lists selected compatible operational amplifiers available from Analog Devices. These operational amplifiers satisfy all the above requirements and in most all cases will not require offset voltage nulling. Table V. Precision Operational Amplifier the DAC16 Model VOS TCVOS IB AVOL OP177 10 µV 0.3 µV/°C 2 nA 12000 V/mV OP77 25 µV 0.6 µV/°C 2.8 nA 2000 V/mV OP27 25 µV 0.3 µV/°C 80 nA 1500 V/mV OP97 25 µV2 µV/°C 0.15 nA 2000 V/mV In high speed applications where resolution is more important than absolute accuracy, operational amplifiers such as the AD843 offer the requisite settling time. Although these amplifi- ers are not specified for 16-bit performance, their settling times are two to three times faster than the DAC16 and will introduce negligible error to the overall circuit’s settling time. It is possible to estimate the 16-bit settling time of an operational amplifier if its 12-bit settling time is known. Assuming that the op amp can be modeled by a single-pole response, then the ratio of the op amp’s 16-bit settling time to its 12-bit settling can be expressed as: t s(16 − bit ) t s(12 − bit ) = 1.33 Since many operational amplifier data sheets provide charts illustrating 0.01% settling time versus output voltage step size, all that is required to estimate an op amp’s 16-bit settling time is to multiply the 12-bit settling time for the required full-scale voltage by 1.33. The circuit’s overall settling time can then be approximated by the root-sum-square method: t S = ( t DAC ) 2 + (t OA ) 2 where tDAC = DAC16’s specified full-scale settling time tOA = Op amp full-scale settling time As a design aid, Table VI illustrates a high speed operational amplifier selector guide for devices compatible with the DAC16 for high speed applications. All these devices exhibit the requi- site settling time, input offset voltage, and input bias current consistent with maximum performance. Table VI. High Speed Operational Amplifiers for the DAC16 Model tS to % VOS TCVOS IB AVOL OP467 200 ns –0.01 0.5 mV 3.5 µV/°C 0.5 µA 20 V/mV AD817 70 ns –0.01 2 mV 10 µV/°C 6.6 µA 6 V/mV AD829 90 ns –0.1 0.5 mV 0.3 µV/°C7 µA 100 V/mV AD841 110 ns –0.01 1 mV 35 µV/°C5 µA 45 V/mV AD843 135 ns –0.01 1 mV 12 µV/°C 0.001 µA 25 V/mV AD845 350 ns –0.01 0.25 mV 5 µV/°C 0.001 µA 500 V/mV AD847 120 ns –0.01 1 mV 15 µV/°C5 µA 5.5 V/mV AD841 6 8 5 100pF M3 11 12 9 M2 3 4 1 M4 75 500pF 510 –15V 169 –5V 249 169 –5V 249 Q1 Q2 –5V +5V T/ H 14 13 16 M1 360 360 +15V INPUT IN4735 MC10124 200 OUTPUT 1.6k 0.39 F 20k –15V TO PIN 2 SD5000 Q1, Q2 = MPS571 M1 – M4 = SD5000 200 Figure 27. A High Performance Deglitching Circuit |
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