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TPS51604DSGR Datasheet(PDF) 10 Page - Texas Instruments |
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TPS51604DSGR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 20 page UDG-12218 VUVLO_H VUVLO_L VVDD Driver On TPS51604 SLUSBA6 – DECEMBER 2012 www.ti.com DETAILED DESCRIPTION The TPS51604 is a synchronous buck MOSFET driver designed to drive both high-side and low-side MOSFETs. It allows high-frequency operation with current driving capability matched to the application. The integrated boost switch is internal. The TPS51604 employs dead-time reduction control and shoot-through protection; which helps avoid simultaneous conduction of high-side and low-side MOSFETs. Also, the drivers improve light-load efficiency with integrated DCM mode operation using adaptive crossing detection. Typical applications yield a steady-state duty cycle of 60% or less. For high steady-state duty cycle applications, including a small external Schottky diode may help to ensure sufficient charging of the bootstrap capacitor. Undervoltage Lockout Protection (UVLO) The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both DRVH and DRVL hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H)., Then the driver becomes operational and responds to PWM and SKIP commands. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of DRVH and DRVL actively low. Figure 15 shows this function. CAUTION Do not start the driver in the very low power mode (SKIP = Tri-state). Figure 15. UVLO Operation PWM Pin The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes. Operation into and out of tri-state mode follows the timing diagram outlined in Figure 16. When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V (typ.) and 5.0 V (typ.) PWM drive signals. When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP pin. Normal operation requires this time period in order for the auto-zero comparator to resume. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS51604 |
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