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OP285GP Datasheet(PDF) 8 Page - Analog Devices |
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OP285GP Datasheet(HTML) 8 Page - Analog Devices |
8 / 16 page REV. A OP285 –8– 16–20V 0.1 F V+ V– 5V D1 D2 +15V 2N4416 D3 D4 OUTPUT (TO SCOPE) 1 F IC2 2N2222A –15V 1N4148 DUT 1/2 OP260AJ 16–20V – + + – SCHOTTKY DIODES D1–D4 ARE HEWLETT-PACKARD HP5082-2835 IC1 IS 1/2 OP260AJ IC2 IS PMI OP41EJ 15k RL 1k 0.1 F 10k 10k RF 2k RG 222 750 1k +15V 3 8 1 4 2 –15V + 7A13 PLUG-IN – 7A13 PLUG-IN 2N3904 300pF 15V 1N4148 TTL INPUT 15V 1.8k 0.1 F VREF (–1V) 2N2907 IOUT |VREF| 1k *NOTE DECOUPLE CLOSE TOGETHER ON GROUND PLAN WITH SHORT LEAD LENGTHS. * 0.01 F 0.47 F + 10 F 0.1 F 0.1 F 220 1k 1k 1.5k 1/2 OP285 + – Figure 5. Transient Output Load Current Test Fixture 10 90 100 0% A1 1,2 V T 138.9NS 5V TTL CTRL (5V/ DIV) 10V VOUT (2MV/ DIV) 2MV 50NS Figure 6. OP285’s Output Load Current Recovery Time Measuring Settling Time The design of OP285 combines high slew rate and wide gain- bandwidth product to produce a fast-settling (ts < l µs) amplifier for 8- and 12-bit applications. The test circuit designed to measure the settling time of the OP285 is shown in Figure 7. This test method has advantages over false-sum node techniques in that the actual output of the amplifier is measured, instead of an error voltage at the sum node. Common-mode settling effects are exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum-node method. Of course, a reasonably flat-top pulse is required as the stimulus. The output waveform of the OP285 under test is clamped by Schottky diodes and buffered by the JFET source follower. The signal is amplified by a factor of ten by the OP260 and then Schottky-clamped at the output to prevent overloading the oscilloscope’s input amplifier. The OP41 is configured as a fast integrator which provides overall dc offset nulling. High Speed Operation As with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. Rec- ommended circuit configurations for inverting and noninverting applications are shown in Figures 8 and Figure 9. +15V + 2 3 8 1 4 VIN VOUT –15V 10 F 0.1 F RL 15k 0.1 F 10 F 1/2 OP285 Figure 8. Unity Gain Follower Figure 7. OP285’s Settling Time Test Fixture |
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