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54VCXH162373 Datasheet(PDF) 1 Page - STMicroelectronics |
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54VCXH162373 Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 18 page August 2011 Doc ID 10653 Rev 7 1/18 18 54VCXH162373 Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs Features ■ 1.65 to 3.6 V inputs and outputs ■ High speed: –tPD = 3.3 ns (Max.) at VCC = 3.0 to 3.6 V –tPD = 4.5 ns (Max.) at VCC = 2.3 to 2.7 V ■ Symmetrical impedance outputs: –|IOH| = IOL = 12 mA (Min.) at VCC = 3.0 V –|IOH| = IOL = 8 mA (Min.) at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ 26 Ω serie resistors in outputs ■ Operating voltage range: –VCC(Opr) = 1.65 V to 3.6 V ■ Pin and function compatible with 54 series HR162373 ■ Bus hold provided on both sides ■ Cold spare function ■ Latch-up performance exceeds 300 mA (JESD 17) ■ ESD performance: – HBM > 2000 V (MIL STD 883 method 3015); MM > 200 V ■ 300 krad Mil1019.6 condition A, (RHA QML qualification extension undergone) ■ No SEL, no SEUand no SET under 110 Mev/cm2/mg LET heavy ions irradiation ■ QML qualified product ■ Device fully compliant with DSCC SMD 5962-05211 ■ 100 mV typical input hysteresis Description The 54VCXH162373 is a low voltage CMOS 16 bit d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and five- layer metal wiring C²MOS technology. It is ideal for low power and very high speed 1.65 to 3.6 V applications; it can be interfaced to 3.6 V signal environment for both inputs and outputs. These 16 bit D-type latches are bite controlled by two latch enable inputs (nLE) and two output enable inputs (OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. The device circuits is including 26 Ω series resistance in the outputs. These resistors permit to reduce line noise in high speed applications. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2 kV ESD immunity and transient excess voltage. Flat-48 The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. www.st.com |
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