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2

Unit Loading/Fan Out

Functional Description

The 74F299 contains eight edge-triggered D-type flip-flops

and the interstage logic necessary to perform synchronous

shift left, shift right, parallel load and hold operations. The

the Mode Select Table. All flip-flop outputs are brought out

through 3-STATE buffers to separate I/O pins that also

are also brought out on other pins for expansion in serial

shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs

and resets the flip-flops. All other state changes are initi-

ated by the rising edge of the clock. Inputs can change

when the clock is in either state provided only that the rec-

ommended setup and hold times, relative to the rising edge

of CP, are observed.

buffers and puts the I/O pins in the high impedance state.

In this condition the shift, hold, load and reset operations

can still occur. The 3-STATE outputs are also disabled by

lel load operation.

Mode Select Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

 = LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic

operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

CP

Clock Pulse Input (Active Rising Edge)

1.0/1.0

20

µA/−0.6 mA

Serial Data Input for Right Shift

1.0/1.0

20

µA/−0.6 mA

Serial Data Input for Left Shift

1.0/1.0

20

µA/−0.6 mA

Mode Select Inputs

1.0/2.0

20

µA/−1.2 mA

MR

Asynchronous Master Reset Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

3-STATE Output Enable Inputs (Active LOW)

1.0/1.0

20

µA/−0.6 mA

Parallel Data Inputs or

3.5/1.083

70

µA/−0.65 mA

3-STATE Parallel Outputs

150/40(33.3)

−3 mA/24 mA (20 mA)

Serial Outputs

50/33.3

−1 mA/20 mA

Inputs

Response

L

X

X

X

HH

H

HL

H

HH

L

H

L

L

X

Hold