© 1999 Fairchild Semiconductor Corporation

DS009468

www.fairchildsemi.com

April 1988

Revised July 1999

74F51

Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate

General Description

This device contains two independent logic units, one per-

forming a 2-2 AND-OR-INVERT and the other performing a

3-3 AND-OR-INVERT function.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Unit Loading/Fan Out

Function Table for 3-Input Gates

Function Table for 2-Input Gates

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Order Number

Package Number

Package Description

74F51SC

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74F51SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F51PC

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names

Description

U.L.

1.0/1.0

20

µA/−0.6 mA

Outputs

50/33.3

−1 mA/20 mA

Inputs

Output

HHH

X

X

X

L

XXX

H

H

H

L

All other combinations

H

Inputs

Output

HHX

X

L

XX

H

H

L

All other combinations

H