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74F899QC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74F899QC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 12 page © 1999 Fairchild Semiconductor Corporation DS010195 www.fairchildsemi.com February 1989 Revised August 1999 74F899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The 74F899 is a 9-bit to 9-bit parity transceiver with trans- parent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 mA at the A-bus and 64 mA at the B-bus. The 74F899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Features s Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in systems applications in place of the 74F543 and 74F280 s May be used in system applications in place of the 74F657 and 74F373 (no need to change T/R to check parity) Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol Order Number Package Number Package Description 74F899SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F899QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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