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74FR240SC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74FR240SC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 5 page © 1999 Fairchild Semiconductor Corporation DS010901 www.fairchildsemi.com October 1991 Revised August 1999 74FR240 Octal Buffer/Line Driver with 3-STATE Outputs General Description The 74FR240 is an inverting octal buffer and line driver designed to be employed as memory and address driver, clock driver and bus oriented transmitter or receiver. Features s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs sink 64 mA and source 15 mA s Guaranteed pin-to-pin skew Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Order Number Package Number Package Description 74FR240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74FR240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74FR240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description OE1, OE2 Output Enable Input (Active-LOW) I0–I7 Inputs O0–O7 Outputs Inputs Outputs OE1 In (Pins 12, 14, 16, 18) LL H LH L HX Z Inputs Outputs OE2 In (Pins 3, 5, 7, 9) LL H LH L HX Z |
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Descripción similar - 74FR240SC |
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