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74FR74SC Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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74FR74SC Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 8 page 5 www.fairchildsemi.com AC Electrical Characteristics 74FR74 Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). tOST is guaranteed by design. AC Operating Requirements 74FR74 Note 4: This specification is guaranteed by design. Symbol Parameter TA = +25°CTA = 0°C to +70°C Units VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 150 190 150 MHz tPLH Propagation Delay 2.5 3.5 5.0 2.5 5.0 ns tPHL CPn to Qn or Qn 2.54.5 6.02.5 6.0 tPLH Propagation Delay 1.5 3.5 5.5 1.5 5.5 ns tPHL CDn or SDn to Qn or Qn 2.05.5 7.02.0 7.0 tOSHL Pin to Pin Skew 1.0 ns (Note 3) for HL Transitions tOSLH Pin to Pin Skew 1.0 ns (Note 3) for LH Transitions tOST Pin to Pin Skew 3.0 ns (Note 3) for HL/LH Transitions tQ/Q True/Complement 1.8 ns (Note 3) Output Skew tPS Pin (Signal) 1.8 ns (Note 3) Transition Variation Symbol Parameter TA = +25°CTA = 0°C to +70°C Units VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF MinMax MinMax tS(H) Setup Time, HIGH or LOW 2.5 2.5 ns tS(L) Dn to CPn 2.5 2.5 tH(H) Hold Time, HIGH or LOW 0 0 ns tH(L) Dn to CPn 00 tW(H) CPn Pulse Width 3.3 3.3 ns tW(L) HIGH or LOW 3.3 3.3 (Note 4) tW(L) SDn or CDn Pulse Width 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns SDn or CDn to CPn |
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