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74LVTH16373MTD Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LVTH16373MTD Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page © 2005 Fairchild Semiconductor Corporation DS012021 www.fairchildsemi.com January 1999 Revised June 2005 74LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs General Description The LVT16373 and LVTH16373 contain sixteen non-invert- ing latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LVTH16373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL inter- face to a 5V environment. The LVT16373 and LVTH16373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16373), also available without bushold feature (74LVT16373) s Live insertion/extraction permitted s Power Up/Power Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 16373 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Note 1: BGA package available in Tape and Reel only. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Order Number Package Number Package Description 74LVT16373GX (Note 1) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVT16373MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16373MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16373GX (Note 1) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVTH16373MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16373MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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