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74LVT573SJ Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LVT573SJ Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Truth Table H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial O0 Previous O0 before HIGH to LOW transition of Latch Enable Functional Description The LVT573 and LVTH573 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs Inputs Outputs LE OE Dn On XH X Z HL L L HL H H LL X O0 |
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