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74VCX16827MTD Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74VCX16827MTD Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Connection Diagram Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Functional Description The 74VCX16827 contains twenty non-inverting buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by Output Enable (OEn) inputs. When OE1, and OE2 are LOW, O0—O10 are in the 2-state mode. When either OE1 or OE2 are HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. The same applies for byte two with OE3 and OE4. Logic Diagrams Inputs Outputs OE1 OE2 I0–I9 O0–O9 LL L L LL H H HX X Z XH X Z Inputs Outputs OE3 OE4 I0–I9 O10–O19 LL L L LL H H HX X Z XH X Z |
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