3

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Mode Select Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

State Diagram

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

MR

PE

CET CEP

Action on the Rising

Clock Edge (

)

L

X

X

X

Reset (Clear)

H

L

X

X

H

H

H

H

Count (Increment)

H

H

L

X

No Change (Hold)

H

H

X

L

No Change (Hold)