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74VHC175SJ Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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74VHC175SJ Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 AC Electrical Characteristics Note 4: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL =| tPHLmax − tPHLmin|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 • n AC Operating Requirements Note 6: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V Symbol Parameter VCC (V) TA = 25°CTA = −40°C to +85°C Units Conditions Min Typ Max Min Max fMAX Maximum Clock 3.3 ± 0.3 90 140 75 MHz CL = 15 pF Frequency 50 75 45 CL = 50 pF 5.0 ± 0.5 150 210 125 MHz CL = 15 pF 85 115 75 CL = 50 pF tPLH Propagation Delay 3.3 ± 0.3 7.5 11.5 1.0 13.5 ns CL = 15 pF tPHL Time (CP to Qn or Qn) 10.0 15.0 1.0 17.0 CL = 50 pF 5.0 ± 0.5 4.8 7.3 1.0 8.5 ns CL = 15 pF 6.3 9.3 1.0 10.5 CL = 50 pF tPLH Propagation Delay Time 3.3 ± 0.3 6.3 10.1 1.0 12.0 ns CL = 15 pF tPHL (MR to Qn or Qn) 8.8 13.6 1.0 15.5 CL = 50 pF 5.0 ± 0.5 4.3 6.4 1.0 7.5 ns CL = 15 pF 5.8 8.4 1.0 9.5 CL = 50 pF tOSLH Output to 3.3 ± 0.3 1.5 1.5 CL = 50 pF tOSHL Output Skew 5.0 ± 0.5 1.0 1.0 CL = 50 pF (Note 4) CIN Input Capacitance 4 10 10 pF VCC = Open CPD Power Dissipation 44 pF (Note 5) Capacitance Symbol Parameter VCC (V) (Note 6) TA = 25°CTA = −40°C to +85°C Units Typ Guaranteed Minimum tW(L) Minimum Pulse Width (CP) 3.3 5.0 5.0 ns tW(H) 5.0 5.0 5.0 tW(L) Minimum Pulse Width (MR) 3.3 5.0 5.0 ns 5.0 5.0 5.0 tS Minimum Setup Time (Dn to CP) 3.3 5.0 5.0 ns 5.0 4.0 4.0 tH Minimum Hold Time (Dn to CP) 3.3 1.0 1.0 ns 5.0 1.0 1.0 tREC Minimum Removal Time (MR) 3.3 5.0 5.0 ns 5.0 5.0 5.0 |
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