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AM60N10-70PCFM Datasheet(PDF) 2 Page - Analog Power |
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AM60N10-70PCFM Datasheet(HTML) 2 Page - Analog Power |
2 / 5 page 2 AM60N10-70PCFM Analog Power PRELIMINARY Publication Order Number: DS-AM60N10-70_B Notes a. Pulse test: PW <= 300us duty cycle <= 2%. b. Guaranteed by design, not subject to production testing. Analog Power (APL) reserves the right to make changes without further notice to any products herein. APL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does APL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in APL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. APL does not convey any license under its patent rights nor the rights of others. APL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the APL product could create a situation where personal injury or death may occur. Should Buyer purchase or use APL products for any such unintended or unauthorized application, Buyer shall indemnify and hold APL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that APL was negligent regarding the design or manufacture of the part. APL is an Equal Opportunity/Affirmative Action Employer. Min Typ Max Gate-Threshold Voltage VGS(th) VDS =VGS, ID =250uA 1 V Gate-Body Leakage IGSS VDS= 0 V, VGS= 20V ±100 nA VDS =80V, VGS =0V 1 VDS= 80 V, VGS= 0 V, TJ = 55 oC 25 On-State Drain Current A ID(on) VDS =5V, VGS =10V 120 A VGS =10V, ID =30A 78 VGS =4.5V, ID =20A 92 Forward Tranconductance A gfs VDS =15V, ID =30A 30 S Diode Forward Voltage VSD IS =34A, VGS =0V 1.1 V Total Gate Charge Qg 8.5 Gate-Source Charge Qgs 3.3 Gate-Drain Charge Qgd 4.0 Turn-On Delay Time td(on) 18 Rise Time tr 59 Turn-Off Delay Time td(off) 37 Fall-Time tf 9 Drain-Source On-Resistance A rDS(on) mΩ Parameter Limits Unit VDD =25V, RL =25Ω , ID =34A, VGEN =10V nS VDS =15V, VGS =4.5V, ID =90A nC Dynamic b SPECIFICATIONS(TA =25 oCUNLESSOTHERWISENOTED) uA IDSS Zero Gate Voltage Drain Current Static Test Conditions Symbol |
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