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UC2879DW Datasheet(PDF) 8 Page - Texas Instruments |
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UC2879DW Datasheet(HTML) 8 Page - Texas Instruments |
8 / 15 page www.ti.com ( ) 2.5 RT 10 mA 1 Dlin = · - ADDITIONAL INFORMATION UC1879 UC2879 UC3879 SLUS230B – JUNE 1998 – REVISED JUNE 2007 PIN DESCRIPTIONS (continued) RT (Clock/Sync Duty Cycle Set Pin): The UC3879 oscillator produces a sawtooth waveform. The rising edge is generated by connecting a resistor from RT to GND and a capacitor from CT to GND (see CT pin description). During the rising edge, the modulator has linear control of the duty cycle. The duty cycle jumps to 100% when the voltage on COMP exceeds the oscillator peak voltage. Selection of RT should be done first, based on the required upper end of the linear duty cycle range (Dlin) as follows: Recommended values for RT range from 2.5 k Ω to 100 kΩ. SS: Connect a capacitor between this pin and GND to set the soft start time. The voltage at SS will remain near zero volts as long as VIN is below the UVLO threshold. Soft start will be pulled up to about 4.8 V by an internal 9- µA current source when VIN and VREF become valid (assuming a non-fault condition). In the event of a current fault (CS voltage exceeding 2.5 V), soft start will be pulled to GND and then ramp to 4.8 V. If a fault occurs during the soft start cycle, the outputs will be immediately disabled and soft start must fully charge prior to resetting the fault latch. For paralleled controllers, the soft start pins may be paralleled to a single capacitor, but the charge currents will be additive. UVSEL: Connecting this pin to VIN sets a turn on voltage of 10.75 V with 1.5 V of UVLO hysteresis. Leaving the pin open-circuited programs a turn on voltage of 15.25 V with 6 V of hysteresis. VC (Output Switch Supply Voltage): This pin supplies power to the output drivers and their associated bias circuitry. The difference between the output high drive and VC is typically 2.1 V. This supply should be bypassed directly to PWRGND with a low ESR/ESL capacitor. VIN (Primary Chip Supply Voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V for normal operation. To ensure proper functionality, the UC3879 is inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should be bypassed directly to GND with a low ESR/ESL capacitor. NOTE: When VIN exceeds the UVLO threshold the supply current (IIN) jumps from about 100 A to greater than 20 mA. If the UC3879 is not connected to a well bypassed supply, it may immediately enter the UVLO state again. Therefore, sufficient bypass capacity must be added to ensure reliable startup. VREF: This pin provides an accurate 5 V voltage reference. It is internally short circuit current limited. VREF is disabled while VIN is below the UVLO threshold. The circuit is also disabled until VREF reaches approximately 4.75 V. For best results bypass VREF with a 0.1 µF, low ESR/ESL capacitor. Please refer to the following Unitrode publications for additional information. The following three topics are available in the Applications Handbook. 1. Application Note U-154, The New UC3879 Phase- Shifted PWM Controller Simplifies the Design of Zero Voltage Transition Full-Bridge Converters, by Laszlo Balogh. 2. Application Note U-136, Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM Controller, by Bill Andreycak. 3. Design Note DN-63, The Current-Doubler Rectifier: An Alternative Rectification Technique for Push-Pull and Bridge Converters, by Laszlo Balogh. 8 Submit Documentation Feedback |
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