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UC3855BDWTRG4 Datasheet(PDF) 5 Page - Texas Instruments |
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UC3855BDWTRG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 17 page 5 UC2855A/B UC3855A/B CS: The reconstructed inductor current waveform gener- ated on the CI pin is level shifted down a diode drop to this pin. Connect the current amplifier input resistor be- tween CS and the inverting input of the current amplifier. The waveform on this pin is compared to the multiplier output waveform through the average current sensing current amplifier. The input to the peak current limiting comparator is also connected to this pin. A voltage level greater than 1.5 volts on this pin will trip the comparator and disable the gate driver output. CT: A capacitor from CT to GND sets the PWM oscillator frequency according to the following equation: f CT ≈ • 1 11200 . Use a high quality ceramic capacitor with low ESL and ESR for best results. A minimum CT value of 200pF in- sures good accuracy and less susceptibility to circuit lay- out parasitics. The oscillator and PWM are designed to provide practical operation to 500kHz. GND: All voltages are measured with respect to this pin. All bypass and timing capacitors connected to GND should have leads as short and direct as possible. GTOUT: The output of the PWM is a 1.5A peak totem pole MOSFET gate driver on GTOUT. A series resistor between GTOUT and the MOSFET gate of at least 10 ohms should be used to limit the overshoot on GTOUT. In addition, a low VF Schottky diode should be connected between GTOUT and GND to limit undershoot and possi- ble erratic operation. IAC: This is a current input to the multiplier. The current into this pin should correspond to the instantaneous value of the rectified AC input line voltage. This is ac- complished by connecting a resistor directly between IAC and the rectified input line voltage. The nominal 650mV level present on IAC negates the need for any additional compensating resistors to accommodate for the zero crossings of the line. A current equal to one fourth of the IAC current forms one of the inductor current synthesizer inputs. IMO: This is the output of the multiplier, and the non- inverting input of the current amplifier. Since this output is a current, connect a resistor between this pin and ground equal in value to the input resistor of the current amplifier. The common mode operating range for this pin is −0.3V to 5V. ION: This pin is the current sensing input. It should be connected to the secondary side output of a current sensing transformer whose primary winding is in series with the boost switch. The resultant signal applied to this input is buffered and level shifted up a diode to the CI ca- pacitor on the CI pin. The ION buffer has a source only output. Discharge of the CI cap is enabled through the current synthesizer circuitry. The current sense trans- former termination resistor should be designed to obtain a 1V input signal amplitude at peak switch current. OVP: This pin senses the boost output voltage through a voltage divider. The enable comparator input is TTL com- patible and can be used as a remote shutdown port. A voltage level below 1.8V, disables VREF, oscillator, and the PWM circuitry via the enable comparator. Between 1.8V and VREF (7.5V) the UC is enabled. Voltage levels above 7.5V will set the PWM latch via the hysteretic OVP comparator and disable both ZVTOUT and GTOUT until the OVP level has decayed by the nominal hysteresis of 400mV. If the voltage divider is designed to initiate an OVP fault at 5% of OV, the internal hysteresis enables normal operation again when the output voltage has reached its nominal regulation level. Both the OVP and enable comparators have direct logical connections to the PWM output and exhibit typical propagation delays of 200ns. REF: REF is the output of the precision reference. The output is capable of supplying 25mA to peripheral cir- cuitry and is internally short circuit current limited. REF is disabled and low whenever VCC is below the UVLO threshold, and when OVP is below 1.8V. A REF “GOOD” comparator senses REF and disables the stage until REF has attained approximately 90% of its nominal value. Bypass REF to GND with a 0.1 µF or larger ce- ramic capacitor for best stability. RVS: The nominal 3V signal present on the VSENSE pin is buffered and brought out to the RVS pin. A current pro- portional to the output voltage is generated by connect- ing a resistor between this pin and GND. This current forms the second input to the current synthesizer. SS: Soft-start VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to in- crease slowly. In the event of a VVCC dropout, the OVP/EN is forced below 1.8V (typ), SS quickly dis- charges to disable the PWM. PIN DESCRIPTIONS (cont.) |
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