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TPS2224ADBRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS2224ADBRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 31 page www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE RECOMMENDED OPERATING CONDITIONS TPS2220A, TPS2223A TPS2224A, TPS2226A SLVS428E – MAY 2002 – REVISED MSRCH 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. over operating free-air temperature range (unless otherwise noted) (1) TPA222xA UNIT VI(3.3V) –0.3 to 5.5 V VI Input voltage range for card power VI(5V) –0.3 to 5.5 V VI(12V) (2) –0.3 to 14 V Logic input/output voltage –0.3 to 6 V VO(xVCC) –0.3 to 6 V VO Output voltage VO(xVPP) –0.3 to 14 V Continuous total power dissipation See Dissipation Rating Table IO(xVCC) Internally Limited IO Output current IO(xVPP) Internally Limited TJ Operating virtual junction temperature range –40 to 100 °C Tstg Storage temperature range –55 to 150 °C OC sink current 10 mA (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Not applicable for TPS2223A TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE(1) POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING 24 890 mW 8.9 mW/ °C 489 mW 356 mW DB 30 1095 mW 10.95 mW/ °C 602 mW 438 mW PWP 24 3322 mW 33.22 mW/ °C 1827 mW 1329 mW (1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface). MIN MAX UNIT VI(3.3V) (1) 3 3.6 Input voltage, VI(3.3V) is required for all circuit operations. 5V and 12V are only required for VI(5V) 3 5.5 V their respective functions. VI(12V) (2) 7 13.5 IO(xVCC) at TJ = 100°C 1 A IO Output current IO(xVPP) at TJ = 100°C 100 mA f(clock) Clock frequency 2.5 MHz Data 200 Latch 250 tw Pulse duration ns Clock 100 Reset 100 th Data-to-clock hold time (see Figure 2) 100 ns tsu Data-to-clock setup time (see Figure 2) 100 ns td(latch) Latch delay time (see Figure 2) 100 ns td(clock) Clock delay time (see Figure 2) 250 ns (1) It is understood that for VI(3.3V) < 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC. (2) Not applicable for TPS2223A 2 Submit Documentation Feedback Copyright © 2002–2008, Texas Instruments Incorporated Product Folder Link(s): TPS2220A TPS2223A TPS2224A TPS2226A |
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