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TPS40054PWPR Datasheet(PDF) 5 Page - Texas Instruments |
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TPS40054PWPR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 35 page 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ILIM VIN BOOST HDRV SW BP10 LDRV PGND KFF RT BP5 SYNC SGND SS/SD VFB COMP Thermal Pad TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 Table 1. PIN DESCRIPTIONS TERMINAL I/O DESCRIPTION NAME NO. Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the SW voltage. A BOOST 14 O 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET. 5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an BP5 3 O external DC load of 1 mA or less. 10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF BP10 11 O ceramic capacitor. This pin may be used with an external DC load of 1 mA or less. Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB COMP 8 O pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large signal transient response. Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW HDRV 13 O (MOSFET off). Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage ILIM 16 I drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage drop (VIN – SW) across the high-side MOSFET during conduction. A resistor is connected from this pin to VIN to program the amount of voltage feed-forward and UVLO level. The KFF 1 I current fed into this pin is internally divided and used to control the slope of the PWM ramp. Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET LDRV 10 O off). Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the PGND 9 lower MOSFET(s). RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. SGND 5 Signal ground reference for the device. Soft-start programming and shutdown pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS/SD pin is used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is SS/SD 6 I approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage (VO) decays while the internal circuitry remains active. This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40054 also SW 12 I uses this pin for zero current sensing. Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. SYNC 4 I If synchronization is not used, connect this pin to SGND. Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference VFB 7 I voltage, 0.7 V. VIN 15 I Supply voltage for the device. PWP PACKAGE (TOP VIEW) A. For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002. B. PowerPAD™ heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins. Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS40054 TPS40055 TPS40057 |
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