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Si3220 Datasheet(PDF) 10 Page - Silicon image |
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Si3220 Datasheet(HTML) 10 Page - Silicon image |
10 / 108 page Si3220/Si3225 10 Rev. 1.0 Table 5. AC Characteristics (VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Test Condition Min Typ Max Unit TX/RX Performance Overload Level 2.5 — — VPK Overload Compression 2-Wire – PCM Figure 6 — — Single Frequency Distortion1 2-Wire – PCM or PCM – 2-Wire: 200Hz to 3.4kHz —— –65 dB PCM – 2-Wire – PCM: 200 Hz – 3.4 kHz, 16-bit Linear mode —— –65 dB Signal-to-(Noise + Distortion) Ratio2 200Hz to 3.4kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZT Figure 5 — — Audio Tone Generator Signal-to- Distortion Ratio2 0 dBm0, Active off-hook, and OHT, any ZT 46 — — dB Intermodulation Distortion — — –41 dB Gain Accuracy2 2-Wire to PCM or PCM to 2-Wire 1014 Hz, Any gain setting –0.25 — +0.25 dB Attenuation Distortion vs. Freq. 0 dBm 0 Figure 7,8 — — — Group Delay vs. Frequency Figure 9 — — — Gain Tracking3 1014 Hz sine wave, reference level –10 dBm Signal level: —— — — 3 dB to –37 dB — — ± 0.25 dB –37 dB to –50 dB — — ± 0.5 dB –50 dB to –60 dB — — ± 1.0 dB Round-Trip Group Delay 1014 Hz, Within same time-slot — 600 700 µs Crosstalk between channels TX or RX to TX TX or RX to RX 0 dBm0, 300Hz to 3.4kHz 300Hz to 3.4kHz — — — — –75 –75 dB dB Gain Step Increment4 Step size around 0 dB — ±0.0005 — dB 2-Wire Return Loss5 200Hz to 3.4kHz 26 30 — dB Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The digital gain block is a linear multiplier that is programmable from – ∞ to +6 dB. The step size in dB varies over the complete range. See “Audio Path Processing”. 5. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients. 6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off- hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application. |
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