8251A

© 2012 Rochester Electronics, LLC. All Rights Reserved 12192012

Specification Number 8251A-CI (I) REV A

Page 1 of 11

Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes

only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves

the right to make changes without further notice to any specification herein.

* For complete Rochester ordering guide, please refer to page 2 *

The 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/T

ransmitter (USART)

designed for data communications with microprocessor families such as MCS-48, 80,

85, and iAPX 86, 88.

The 8251A is used as a peripheral device and is programmed by the CPU to operate using

virtually any serial

data transmission technique presently in use (including IBM “bi-sync”). The USART accepts

data characters

from the CPU in parallel format and then converts them into a continuous serial data stream

for transmission.

Simultaneously, it can receive serial data streams and convert them into parallel data characters

for the CPU.

The USART will signal the CPU whenever it can accept a new character for transmission

or whenever it has

received a character for the CPU. The CPU can read the complete status of the USAR

T at any time. These

include data transmission errors and control signals such as SYNDET, TxEMPTY. The chip

is fabricated using

Intel’s high performance HMOS technology.