14

14-b

DACA

14-b

DACB

Control Interface

Clock Distribution

QMC

A-offset

QMC

B-offset

EXTIO

BIASJ

IOUTAP

IOUTAN

IOUTBP

IOUTBN

VDDA33

LVPECL

LVDS

LVPECL

LVDS

LVDS

14

DACB

Gain

Programmable

Delay

1. 2 V

Reference

DACCLKP

DACCLKN

DATACLKP

DATACLKN

DATA13P

DATA13N

SYNCP

SYNCN

ALIGNP

ALIGNN

DATA0P

DATA0N

LVDS

DACA

Gain

Optional Input

DAC3174

SLAS837A – APRIL 2013 – REVISED MAY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BLOCK DIAGRAMS

Figure 1. 14-Bit Interface Mode

2

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