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SI8420SV-C-IS Datasheet(PDF) 7 Page - Silicon Laboratories |
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SI8420SV-C-IS Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 30 page Si8410/20/21 Rev. 1.4 7 Figure 1. Propagation Delay Timing Si8410Bx, Si8420Bx, Si8421Bx Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns Pulse Width Distortion |tPLH - tPHL| PWD See Figure 1 — 1.5 2.5 ns Propagation Delay Skew2 tPSK(P-P) —2.0 3.0 ns Channel-Channel Skew tPSK —0.5 1.8 ns All Models Output Rise Time tr CL = 15 pF — 3.8 5.0 ns Output Fall Time tf CL = 15 pF — 2.8 3.7 ns Common Mode Transient Immunity CMTI VI =VDD or 0 V — 25 — kV/µs Start-up Time3 tSU —15 40 µs Table 3. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA =–40 to 125ºC) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Typical Input tPLH tPHL Typical Output tr tf 90% 10% 90% 10% 1.4 V 1.4 V |
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