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CAT28C16AN-12T Datasheet(PDF) 5 Page - ON Semiconductor

No. de pieza CAT28C16AN-12T
Descripción Electrónicos  16 kb CMOS Parallel EEPROM
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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CAT28C16AN-12T Datasheet(HTML) 5 Page - ON Semiconductor

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CAT28C16A
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5
DEVICE OPERATION
Read
Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The
data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to
eliminate bus contention in a system environment.
Figure 4. Read Cycle
ADDRESS
DATA OUT
DATA VALID
DATA VALID
HIGH−Z
tOHZ
tHZ
tAA
tOH
tOE
tOLZ
tCE
tLZ
tRC
VIH
CE
OE
WE
Figure 5. Byte Write Cycle [WE Controlled]
ADDRESS
DATA OUT
DATA IN
DATA VALID
HIGH−Z
WE
OE
CE
tAH
tAS
tCS
tCH
tWP
tOES
tOEH
tDL
tDS
tDH
tWC
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 10 ms.


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