AD5547-EP datasheet(4/12 Pages) AD

No. de pieza	AD5547-EP

Descripción Electrónicos	Dual-Current Output, Parallel Input

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Fabricante Electrónico	AD [Analog Devices]

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AD5547-EP

Data Sheet

Rev. 0 | Page 4 of 12

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

AC CHARACTERISTICS4

Output Voltage Settling Time

tS

To ±0.1% of full scale, data cycles from zero scale

to full scale to zero scale

0.5

μs

Reference Multiplying Bandwidth

BW

VREF = 100 mV rms, data = full scale

6.8

MHz

DAC Glitch Impulse

Q

VREF = 0 V, midscale – 1 to midscale

−3.5

nV-s

Multiplying Feedthrough Error

VOUT/VREF

VREF = 100 mV rms, f = 10 kHz

−78

dB

Digital Feedthrough

QD

WR = 1, LDAC toggles at 1 MHz

7

nV-s

Total Harmonic Distortion

THD

VREF = 5 V p-p, data = full scale, f = 1 kHz

−104

dB

Output Noise Density

eN

f = 1 kHz, BW = 1 Hz

12

nV/√Hz

Analog Crosstalk

CAT

Signal input at Channel A and measures the

output at Channel B, f = 1 kHz

−95

dB

1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device RFB terminal is

tied to the amplifier output. The +IN pin of the OP97 is grounded, and the IOUT of the DAC is tied to the OP97’s −IN pin. Typical values represent average readings

measured at 25°C.

2 Guaranteed by design; not subject to production testing.

3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V.

4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used.

Timing Diagram

tWR

tDS

tDH

tLWD

tLDAC

tRS

WR

DATA

LDAC

RS

Figure 3. AD5547-EP Timing Diagram

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