DAC101C081, DAC101C081Q, DAC101C085

SNVS801A – APRIL 2012 – REVISED MARCH 2013

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AC and Timing Characteristics

Units

Symbol

Parameter

(Limits)

100h to 300h code change

4.5

6

µs (max)

SR

Output Slew Rate

1

V/µs

Glitch Impulse

Code change from 200h to 1FFh

12

nV-sec

Digital Feedthrough

0.5

nV-sec

160

kHz

70

dB

input frequency = 10kHz

0.8

µsec

Wake-Up Time

0.5

µsec

DIGITAL TIMING SPECS (SCL, SDA)

Standard Mode

100

kHz (max)

Fast Mode

400

kHz (max)

Serial Clock Frequency

3.4

MHz (max)

1.7

MHz (max)

Standard Mode

4.7

µs (min)

Fast Mode

1.3

µs (min)

SCL Low Time

160

ns (min)

320

ns (min)

Standard Mode

4.0

µs (min)

Fast Mode

0.6

µs (min)

SCL High Time

60

ns (min)

120

ns (min)

Standard Mode

250

ns (min)

Data Setup Time

Fast Mode

100

ns (min)

High Speed Mode

10

ns (min)

0

µs (min)

Standard Mode

3.45

µs (max)

0

µs (min)

Fast Mode

0.9

µs (max)

Data Hold Time

0

ns (min)

70

ns (max)

0

ns (min)

150

ns (max)

Standard Mode

4.7

µs (min)

Setup time for a start or a repeated

Fast Mode

0.6

µs (min)

start condition

High Speed Mode

160

ns (min)

Standard Mode

4.0

µs (min)

Hold time for a start or a repeated start

Fast Mode

0.6

µs (min)

condition

High Speed Mode

160

ns (min)

Bus free time between a stop and start

Standard Mode

4.7

µs (min)

condition

Fast Mode

1.3

µs (min)

Standard Mode

4.0

µs (min)

Setup time for a stop condition

Fast Mode

0.6

µs (min)

High Speed Mode

160

ns (min)

(1)

(2)

Quality Level).

(3)

This parameter is ensured by design and/or characterization and is not tested in production.

(4)

Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the

DAC Register will digitally attenuate the signal at Vout.

8

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