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TPL5100DGST Datasheet(PDF) 5 Page - Texas Instruments

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No. de pieza TPL5100DGST
Descripción Electrónicos  TPL5100 Nano Power Programmable Timer with MOS driver
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

TPL5100DGST Datasheet(HTML) 5 Page - Texas Instruments

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TPL5100
www.ti.com
SNAS629B – JULY 2013 – REVISED AUGUST 2013
Electrical Characteristics
(1)
Specifications with standard typeface are for TA =TJ = 25°C, VDD-GND=2.5V, unless otherwise stated.
Symbol
Parameter
Conditions
Min(2)
Typ(3)
Max(2)
Units
POWER SUPPLY
IVDD
Supply current(4)
PGOOD=VDD
30
50
nA
PGOOD=GND
12
nA
TIMER
tDP
Timer Delay Period
16, 32, 64,
100, 128,
s
256, 512,
1024
Timer Delay Period drift over life time(5)
0.06
%
Timer Delay Period drift over temperature
400
ppm/°C
tCAL
Calibration pulse width
14.063
15.625
17.188
ms
tDP to tCAL matching error
(6)
VDD<=3.0V
0.1
%
tDONE
DONE Pulse width(6)
100
ns
tMOS_DRV
MOS_DRV Pulse width
31.25
ms
DIGITAL LOGIC LEVELS
VIH
Logic High Threshold
PGOOD, DONE
0.7xVDD
V
VIL
Logic Low Threshold
PGOOD, DONE
0.3xVDD
V
MOS_DRV, TCAL
VDD-0.3
V
Iout = 100uA
VOH
Logic output High Level
MOS_DRV, TCAL
VDD-0.7
V
Iout = 1mA
MOS_DRV, TCAL
0.3
V
Iout = -100uA
VOL
Logic output Low Level
MOS_DRV, TCAL
0.7
V
Iout = -1mA
TIMING TCAL, MOS_DRV, DONE, PGOOD - Refer to Timing Diagram
trTCAL
Rise Time TCAL
Capacitve load 15pF
50
ns
tfTCAL
Fall Time TCAL
Capacitve load 15pF
50
ns
trMOS_DRV
Rise Time MOS_DRV
Capacitve load 50pF
4
ns
tfMOS_DRV
Fall Time MOS_DRV
Capacitve load 50pF
50
ns
tDDONE
DONE to MOS_DRV delay
Min delay
100
ns
Max delay
tDP-5*tCAL
ms
tDTCAL
TCAL to MOS_DRV delay
tCAL/2
ms
(1)
Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2)
Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(3)
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4)
The supply current doesn’t take in account load and pull-up resistor current. Input pins are at GND or VDD.
(5)
Operational life time test procedure equivalent to 10 years.
(6)
Guaranteed by design.
Copyright © 2013, Texas Instruments Incorporated
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