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CS82C52 Datasheet(PDF) 6 Page - Intersil Corporation |
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CS82C52 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 20 page  6 FN2950.3 April 26, 2006 The Prescaler design has been optimized to provide standard baud rates using any one of three popular crystal frequencies. By using one of these common system clock frequencies, 1.8432MHz, 2.4576MHz or 3.072MHz and Prescaler divide ratios of ÷3, ÷4, or ÷5 respectively, the Prescaler output will provide a constant 614.4KHz. When this frequency is further divided by the Divisor Select counter, any of the standard baud rates from 50 Baud to 38.4Kbaud can be selected (see Table 2). Non-standard baud rates up to 1Mbaud can be selected by using different input frequencies (crystal or an external frequency input up to 16MHz) and/or different Prescaler and Divisor Select ratios. Regardless of the baud rate, the baud rate generator provides a clock which is 16 times the desired baud rate. For example, in order to operate at a 1Mbaud data rate, a 16MHz crystal, a Prescale rate of ÷1, and a Divisor Select rate of “external” would be used. This would provide a 16MHz clock as the output of the Baud Rate Generator to the Transmitter and Receiver circuits. The CO select bit in the BRSR selects whether a buffered version of the external frequency input (IX input) or the Baud Rate Generator output (16x baud rate clock) will be output on the CO output (pin 21). The Baud Rate Generator output will always be a 50% nominal duty cycle except when “external” is selected and the Prescaler is set to ÷3 or ÷5. NOTE: These baud rates are based upon the following input frequency/ Prescale divisor combinations. 1.8432MHz and Prescale = ÷ 3 2.4576MHz and Prescale = ÷ 4 3.072MHZ and Prescale = ÷ 5 † All baud rates are exact except for: Modem Control Register The MCR is a general purpose control register which can be written to and read from. The RTS and DTR outputs are directly controlled by their associated bits in this register. Note that a logic one asserts a true logic level (low) at these output pins. The Interrupt Enable (INTEN) bit is the overall control for the INTR output pin. When INTEN is false, INTR is held false (low). The Operating Mode bits configure the 82C52 into one of four possible modes. “Normal” configures the 82C52 for normal full or half duplex communications. “Transmit Break”' enables the transmitter to only transmit break characters (Start, Data and Stop bits all are logic zero). The Echo Mode causes any data that is received on the SDI input pin to be retransmitted on the SDO output pin. Note that this output is D7 D6 D5 D4 D3 D2 D1 D0 Prescaler Select 00 = ÷ 1 01 = ÷ 3 10 = ÷ 4 11 = ÷ 5 Divisor Select 00000 = ÷ 2 00001 = ÷ 4 00010 = ÷ 16/3 00011 = ÷ 8 00100 = ÷ 32/3 00101 = ÷ 16 00110 = ÷ 58/3 00111 = ÷ 22 01000 = ÷ 32 01001 = ÷ 64 01010 = ÷ 128 01011 = ÷ 192 01100 = ÷ 256 01101 = ÷ 288 01110 = ÷ 352 01111 = ÷ 512 10000 = ÷ 768 11111 = External ( ÷ 1) CO Select 0 = IX Output 1 = Brg Output (On Reset, D7 (CO Select) is Reset to 0) FIGURE 2. BRSR TABLE 2. BAUD RATE DIVISOR 38.4K External 19.2K 2 9600 4 7200 16/3 4800 8 3600 32/3 2400 16 2000† 58/3 1800† 22 1200 32 600 64 300 128 200 192 150 256 134.5† 288 110† 352 75 512 50 768 BAUD RATE ACTUAL PERCENT ERROR 1800 1745.45 3.03% 2000 1986.2 0.69% 134.5 133.33 0.87% 110 109.09 0.83% 82C52 82C52 |
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