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SI5315B-C-GM Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI5315B-C-GM Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 54 page Si5315 Rev. 1.0 9 LVCMOS Output Pins Rise/Fall Times tRF CLOAD = 20 pf See Figure 2 —25 — ns LOSn Trigger Window LOSTRIG From last CKINn to internal detection of LOSn —— 750 µs Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Assume Fold=Fnew, Stable XA-XB reference —10 — ms PLL Performance Output Clock Skew tSKEW of CKOUTn to CKOUTn — — 100 ps Phase Change Due to Temperature Variation tTEMP Maximum phase change from –40 to +85 °C — 300 500 ps Lock Time tLOCKHW RST with valid CKIN to LOL; BW = 100 Hz — 1200 — ms Closed Loop Jitter Peaking JPK —0.05 0.1 dB Jitter Tolerance JTOL See 4.2.3. "Jitter Toler- ance" on page 18. ns pk- pk Minimum Reset Pulse Width tRSTMIN 1— — µs Output Clock Initial Phase Step tP_STEP During clock switch CKIN > 19.44 MHz — 100 200 ps Holdover Frequency Historical Averaging Time tHISTAVG —6.7 — sec Holdover Frequency Historical Delay Time tHISTDEL —26.2 — ms Spurious Noise SPSPUR Max spur @ n x f3 (n > 1, n x f3 < 100 MHz) —–75 — dBc Table 3. AC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units Notes: 1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 µs. 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade. |
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