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TPS40054PWP Datasheet(PDF) 8 Page - Texas Instruments

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No. de pieza TPS40054PWP
Descripción Electrónicos  WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER
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Fabricante Electrónico  TI [Texas Instruments]
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TPS40054PWP Datasheet(HTML) 8 Page - Texas Instruments

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FEED-FORWARD IMPEDANCE
vs
SWITCHING FREQUENCY
fSW - Switching Frequency - kHz
VIN = 25 V
VIN = 15 V
VIN = 9 V
fSW - Switching Frequency - kHz
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
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TPS40054
TPS40055
TPS40057
SLUS593H – DECEMBER 2003 – REVISED JULY 2012
www.ti.com
VKFF is the voltage at the KFF pin (typical value is 3.48 V)
(2)
The curve showing the RKFF required for a given switching frequency, fSW, and VUVLO is shown in Figure 3.
For low-input voltage and high duty-cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltage. For more information on large duty cycle operation, refer to Application Note
(SLUA310), Effect of Programmable UVLO on Maximum Duty Cycle.
Figure 2.
Figure 3.
UVLO OPERATION
The TPS4005x uses variable (user-programmable) UVLO protection. See the Programming the Ramp Generator
section for more information on setting the UVLO voltage. The UVLO circuit holds the soft-start low until the input
voltage has exceeded the user-programmable undervoltage threshold.
The TPS4005x uses the feed-forward pin, KFF, as a user-programmable low-line UVLO detection. This variable
low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage
condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude.
The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The
KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor
can be referenced to the oscillator frequency as descibed in Equation 2.
The programmable UVLO function uses a three-bit counter to prevent spurious shut-downs or turn-ons due to
spikes or fast line transients. When the counter reaches a total of seven counts in which the ramp duration is
shorter than the clock cycle, a powergood signal is asserted and a soft-start initiated, and the upper and lower
MOSFETS are turned off.
Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).
8
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Product Folder Link(s): TPS40054 TPS40055 TPS40057


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