Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD7450ARZ-REEL7 Datasheet(PDF) 10 Page - Analog Devices |
|
AD7450ARZ-REEL7 Datasheet(HTML) 10 Page - Analog Devices |
10 / 22 page –10– AD7450 CIRCUIT INFORMATION The AD7450 is a fast, low power, single-supply, 12-bit successive approximation analog-to-digital converter (ADC). It can operate with a 5 V and 3 V power supply and is capable of throughput rates up to 1 MSPS and 833 kSPS when supplied with an 18 MHz or 15 MHz clock, respectively. This part requires an external reference to be applied to the VREF pin, with the value of the reference chosen depending on the power supply and what suits the application. When operated with a 5 V supply, the maximum reference that can be applied to the part is 3.5 V, and when operated with a 3 V supply, the maximum reference that can be applied to the part is 2.2 V. (See the References section.) The AD7450 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface that is housed in either an 8-lead SOIC or µSOIC package. The serial clock input accesses data from the part and also provides the clock source for the successive approximation ADC. The AD7450 features a power-down option for reduced power consumption between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. CONVERTER OPERATION The AD7450 is a successive approximation ADC based on two capacitive DACs. Figures 3 and 4 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. CAPACITIVE DAC VIN+ VIN– B B A A SW1 SW2 SW3 CS CS + – COMPARATOR CAPACITIVE DAC CONTROL LOGIC Figure 3. ADC Acquisition Phase When the ADC starts a conversion (Figure 4), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the con- version begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the VIN+ and VIN– pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. CAPACITIVE DAC VIN+ VIN– B B A A SW1 SW2 SW3 CS CS + – COMPARATOR CAPACITIVE DAC CONTROL LOGIC Figure 4. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding for the AD7450 is two’s complement. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSB, and so on), and the LSB size is 2 VREF / 4096. The ideal transfer characteristic of the AD7450 is shown in Figure 5. ANALOG INPUT (VIN+ – VIN–) 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 1LSB = 2 VREF/4096 –VREF + 1LSB 0LSB +VREF – 1LSB Figure 5. Ideal Transfer Characteristics TYPICAL CONNECTION DIAGRAM Figure 6 shows a typical connection diagram for the AD7450 for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The VREF pin is connected to either a 2.5 V or a 1.25 V decoupled reference source, depending on the power supply, to set up the analog input range. The common-mode voltage has to be set up exter- nally and is the value that the two inputs are centered on. For more details on driving the differential inputs and setting up the common mode, see the Driving Differential Inputs section. The conversion result for the ADC is output in a 16-bit word consisting of four leading zeros followed by the MSB of the 12-bit result. For applications where power consumption is of concern, the power-down mode should be used between conversions, or bursts of several conversions, to improve power performance. See Modes of Operation section. Rev. A |
Número de pieza similar - AD7450ARZ-REEL7 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |